A new plasma-based copper etching process for future nano devices and circuits
Copper (Cu) is an important interconnection material in high performance integrated circuit (IC) devices due to its high electric conductivity, high resistance to electron migration, and lack of hillocks formation.[i] When Cu is used with a low dielectric constant, low k, material in the multilevel interconnect structure, the circuit speed can be increased several times due to the reduction of the RC delay.[ii] However, Cu is difficult to etch into fine patterns with the conventional plasma etch method because the reaction product is non-volatile under the conventional plasma condition. For the fabrication of ultra large-scale integration circuits (ULSIC), the chemical-mechanical polishing (CMP) process, e.g., damascene or dual damascene method, is the only feasible method to define small-geometry Cu patterns. However, the CMP process is complicated and has inherent limitations in the sub 100 nm node.19 If Cu can be etched into fine lines with a conventional plasma etching process, the multilevel structure could be easily fabricated with the method similar to that of the multilevel aluminum structure. There have been many studies on plasma etching of Cu focusing on how to evaporate nonvolatile etch product in the plasma chamber by adding extra energies, such as substrate heating, UV, IR, laser, or high density ECR source, into the plasma etching system. However, these are impractical for wafer fabrication due to drawbacks such as poor uniformity over a large area or poor process control.
Recently, Kuo and Lee reported a new Cu etching method based on a novel plasma-copper reaction.[iii],[iv],[v],[vi] In this reaction, the plasma exposed Cu film was converted into a compound that was non-volatile and remained on the substrate surface. This compound was subsequently dissolved in a dilute hydrochloric (HCl) solution. Sub micron Cu fine lines were successfully defined by this method, as shown in Figure 4.[vii] The Cu reaction rate was very high, e.g., > 300 nm/min at room temperature. The reactor has a simple parallel-plate electrode configuration. The plasma condition is similar to that of a conventional RIE process.
Figure 4: 0.8-Micrometer Cu line etched with the new plasma-based process.24
Although the submicrometer Cu lines are adequate for current and the next generation IC design, nano-width Cu lines are necessary for future nano transistors. Although many optical and non-optical lithography methods for the definition of nano patterns are under development, e-beam lithography is best suited for this project because of its flexibility and well developed characteristics. The availability of e-beam lithography is critical to the success of the new plasma-based copper etching process, and, therefore, to the development of nano transistor-based ICs.
[i] S.P. Murarka, Metallization-Theory and Practice for VLSI and ULSI, Butterworth-Heinemann, Stoneham, MA, 1993.
[ii] National Technology Roadmap for Semiconductors (NTRS), Semiconductor Industry Association, 1997 and revised in 1999.
[iii] Y. Kuo and S. Lee, Jpn. J. Appl. Phys. Part II, 39, L188, (2000).
[iv] Y. Kuo and S. Lee, Y. Kuo and S. Lee, Appl. Phys. Lett., 78, 1002 (2001).
[v] S. Lee and Y. Kuo, J. Electrochem Soc, 148, G524 (2001).
[vi] S. Lee and Y. Kuo, Jpn. J. Appl. Phys., Part I(12), 41, 7345 (2002).
[vii] S. Lee and Y. Kuo, to appear in ECS Proc. 14th Plasma Processing, 2002.